Shrinking geometries, new manufacturing paradigms, exploding file sizes…
It’s time to rethink everything.

XYALIS increases the productivity, reliability, and capability of dummy fill with GOTstyle, a redesigned fill engine that handles the largest designs with maximum performance and minimum memory requirements thanks to the new GDSII & OASIS (GOT) data representation engine tailored to leverage native OASIS.MASK optimizations.

To increase manufacturing yield, designers must ensure a uniform pattern repartition over chips and wafers. Dummy tiles must be inserted in low-density design areas, to help flatten the surface of each metal layer before CMP. These additional polygons, though electrically inactive, may cause parasitic effects that must be minimized and taken into account early in the design process to avoid behavioral and timing issues.

  • Advanced insertion algorithm with minimal result file size
  • Parasitic effect minimization
  • Support for dual- and quad-patterning
  • Complex dummy tiles instantiation
  • Tile interconnection
  • Staged insertion for complex fill operations and high performance parallelization


GOTstyle redesigned fill engine optimizes new fill methodologies required for the most advanced processes, including dual- and quad-patterning. GOTstyle maximizes CMP yield with a highly accurate patented tile insertion algorithm based on local density and roughness calculations and their variations over large areas.

GOTstyle minimizes parasitic effects by limiting the number of dummy structures and positioning them away from active geometries. Balancing dummy tile insertion around critical nets allows for precise control of impact on timing.

GOTstyle is ideally suited for processes, where uniform density and minimum file size are desirable. It is easy to use but offers complex inter-layer and geometry spacing options, and its metal filling specific engine offers advanced features not available to multi-purpose DRC tools, such as custom fill shapes, dummy stacking and grounding, and uniform distribution along non-orthogonal grids.


  • Maximize CMP yield with highly accurate tile insertion based on local measurements of density and roughness, and their variation over large areas,
  • Minimize parasitic effects by limiting the number of inserted tiles, and positioning them away form critical active geometries,
  • Easy setup, as it does not require a fully qualified process model from the foundry,
  • Take into account impact of dummy tile insertion early in the design process, thanks to fast computation,
  • Compatible with existing DRC flows.


  • Accurate Density and Roughness Analysis
  • Keep Away Function
  • Uniform Dummy Distribution
  • Insert any Type of Dummies
  • High Performance and Low Memory Usage
  • User-friendly Interface