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Very deep sub-micron technologies require that process related issues are taken into account during design.

Starting with 130nm processes, a Chemical Mechanical Polishing (CMP) step has been adopted in the manufacturing process to flatten wafer surface between each metal layer.

Designers have to insert “dummy tiles” into empty areas of their design to help flatten the surface for each metal layer, since metal density variations badly impact the CMP process.

This step, called metal filling or planarization, is necessary for most advanced processes to increase the foundry yield.

While non uniform feature density causes CMP to over-polish empty area, and under-polish dense areas, resulting in degraded performance, the insertion of dummy tiles ensures a uniform pattern repartition over the chips and wafers, thus an increased factory yield.

These additional polygons, though electrically inactive, may add parasitic effects, which must be taken into account early in the design process to ensure correct behavior and timing of the chip.

GTsmooth is a model-based dummy fill solution, which uses topology simulation algorithms to determine the least amount of dummy fill necessary to achieve optimal wafer planarization while minimizing parasitic effects.

Traditional multi-purpose Design Rules Checkers (DRCs) often fill empty areas in metal layers with the maximum number of dummy tiles, leading to degraded performance induced by metal-to-metal and layer-to-layer effects.

GTsmooth performs metal filling in two steps: at first a rule-based method is used to insert as much metal fill as possible, while respecting design rules.

Then a second step, based on a process-specific topology simulation, removes as many fill patterns as possible.

This results in a reduction of up to 95% filling, leading in turn to dramatically reduced parasitics and timing issues.

GTsmooth is ideally suited for the most ambitious designs, which cannot afford any performance impact due to the metal filling step.


Benefits

  • Maximize factory yield with highly accurate tile insertion based on local chip thickness variation,
  • Minimize parasitic effects by limiting to a minimum the number of inserted tiles,
  • High flexibility with process independent thickness estimation fully customizable by user,
  • Take into account impact of dummy tile insertion early in the design process, thanks to fast computation,
  • Compatible with existing DRC flows.

Features

  • User defined thickness estimation function
  • Keep Away Function
  • Uniform Dummy Distribution
  • Insert any Type of Dummies
  • High Performance and Low Memory Usage
  • User-friendly Interface