Multi Chip Project editor

Multi-Project Chips or Wafers (MPC or MPW or mask shuttles) are becoming more popular and, lead to new challenges in layout finishing:

Managing huge and heterogeneous databases
Floorplanning and assembling large databases which cannot be managed by current layout editor or IC floorplanner
Taking into account manufacturing issues

Current designs generate larger databases that become increasingly difficult to process. MPW are made up of blocks from different providers. This can yield to database consistency problems, which need to be detected before tape-out. Furthermore foundry throughput requirements and ever shrinking Time-To-Market demand fastest layout processing.

Main features

Graphical floorplanning and assembly tool for MPW or MPC or shuttles.
Automatic compaction and alignment of chips on a user-defined grid
Automatic placement with area optimization and/or sawing lanes
optimization
Hierarchy and original database preservation
Optional renaming of cells for data-base consistency and avoiding conflicts
Possibility to group and freeze a subset of chips and manipulate them as easily as a single chip
Possibility to build arrays of chips
Support of "cut & paste" through different projects for reuse
Automatic exclusion of sawing lanes in metal filling process
Intelligent selection of chips within an assembly
Full documentation generation in PDF or XML format
64 bits support on SOLARIS 2.8 and HPUX 11.0 for files of more than 2Gb

Key benefits

GTmuch is a graphical tool dedicated to floorplanning and assembly of multiple GDSII/OASIS databases for MPW or MPC:

Improve density/die size
Safe handling and assembly of large databases
Understand/handle manufacturing issues
Maximize number of produced chips in MPWs with sawing line
placement driven
Increase manufacturability with metal filling capabilities

Performance 

GTmuch is able to place hundreds of chips in minutes.
GTmuch is used in production since 2000.

Technology

Based on a graphical editor, GTmuch comes with a comprehensive suite of layout finishing tools:

A GDSII/OASIS file integrity checker which warrants each contribution of the project
A GDSII/OASIS database merging program
A dummy tiles filling program which operates only on empty areas between chips
A virtual chip generator to anticipate floorplaning construction
An optional module for frame generation
An optional GDSII/OASIS viewer

Supported platforms

SUN Sparc Stations, 32 and 64 bits, Solaris 2.5 and + HP HPUX 11.x x86 PC Linux RedHat 3 and + x86-64 PC Linux RedHat 3 and + ItaniumII Linux RedHat 3 and +