High performance "dummy" tiles generator

With the emergence of SOC and increasing design complexity, layout finishing cope with new challenges.
Current designs generate larger databases that become increasingly difficult to process and foundry throughput requirements and ever shrinking Time-To-Market demand fastest layout processing.
Existing multi-purpose layout finishing tools, such as Design Rules Checkers are no longer able to address the issues of today's largest designs.
Very Deep Sub-Micron technologies require that process related issues must be taken into account during the design. Dummy tile insertion, necessary for most advanced processes to increase the foundry yield, has an impact on design performance by creating noise, coupling and extra capacitance to functional signals.

Main features

World fastest tool
Hierarchical management
Layer and datatype management
Layer generation or cell instanciation
Optimized disk management

Key benefits

With GTtiler, dummy fill insertion is no longer a lengthy process that delay your transfer to silicon. You are now able to process the GDSII databases of the largest designs, with the highest performance ever.

The impact of dummy tiles insertion in your design is not negligible. Dummy tiles interfere with functional signals. They may create noise, coupling, extra capacitance effects, and affect overall performance of your design. These are usually not taken into account in your sign-off simulation, as dummy tiles are usually inserted after tape-out. The exceptional performance of GTtiler and its easy integration in design flows, allow you to take into account the impact of dummy tile insertion early in the design cycle. Costly errors can be avoided before the transfer to silicon.

Flow design

Technology

In most deep sub-micron technologies, it becomes mandatory to have a uniform repartition of the patterns on the silicon to increase the factory yield. With non uniform feature density, Chemical-Mechanical Polishing (CMP) causes overpolishing of empty areas (dishing)  and underpolishing of dense areas. Modern foundry rules specify layout density bounds to minimize impact of CMP on yield. Thus, empty areas must be filled with dummy tiles. GTtiler is the first commercial tool to address the dummy tile problem with unprecedented performance.

GTtiler makes a uniform repartition of patterns on the silicon by inserting dummy tiles in your GDSII file. GTtiler either instanciates a cell or directly creates polygons to fill the holes (metal fill or dummy fill). In any case, the hierarchical management allows you to stop the process at any level of the hierarchy. The user may choose the geometry or shape of the tiles instanciated by GTtiler.

GTtiler technology

GTtiler preserves your GDSII database consistency. Starting from your GDSII database, GTtiler fills empty areas either with dummy tile geometry in the layer you specify or by adding dummy cells to your design. The result is a new GDSII file. No layer map is required, as all information about tiles are given as an option in the command line.

GTtiler computes the minimal number of tile arrays necessary to fill the empty areas resulting in a GDSII file of minimal size.

GTtiler performance

GTtiler has been optimized in terms of speed, memory and disk usage.
GTtiler is able to manage the largest databases. Special algorithms have been developed which keep the memory needs close to the GDSII file size. For example, a 100 Mbytes file will use about 100 Mbytes of RAM to be fully processed. In the same way, all the procedures have been carefully reviewed and optimized to shorten execution time. To minimize the disk requirements, GTtiler directly operates on zipped or compressed files.

Supported platforms

SUN Sparc Stations, 32 and 64 bits, Solaris 2.5 and + HP HPUX 11.x x86 PC Linux RedHat 3 and + x86-64 PC Linux RedHat 3 and + ItaniumII Linux RedHat 3 and +