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Minimizing die fracture in three-dimensional IC

XYALIS, in collaboration with Mosis, has published an article about “Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns”. This result has been presented in the SPIE Advanced Lithography + Patterning, San Jose, California, …

Single-pass frame generation for multi-layer 3D circuits

XYALIS, in collaboration with ST Microelectronics,  has published an article about a new methodology to automatically build a single-pass frame for multi-layer 3D circuits.This new methodology uses our frame generation tool GOTframe. This result has been presented in the SPIE Photomask …

November’22: New Release

Grenoble – November 30th, 2022 – Today XYALIS unveils a new release bringing powerful improvements in the frame generation engine (GOTframe) and other tools. GOTframe – Frame Assembly Generation Engine Add new ordering items possibilities. Add new centering items capabilities. …

XYALIS at SPIE Photomask 2022 : Single-pass frame generation for multi-layer 3D circuits

XYALIS will present a paper about “Single-pass frame generation for multi-layer 3D circuits” at the poster session. This paper presents a novel approach to automatically build frames for 3D chips. These chips may be obtained by stacking multiple dies, but …

Geometric based signature – EU patent issuance

Grenoble – July 19th, 2022 – XYALIS,  is proud to announce that the European Patent Office (EPO) has granted our European patent EP3740889B1 (June 22, 2022). In this patent, XYALIS provides a new method to compare layout databases using a geometric based signature. Patent …



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