XYALIS new version of GTmuch makes multi-chip modules and multi-project wafers even easier

Paris, France – Xyalis has announced a major upgrade to GTmuch, the company’s graphical tool dedicated to floorplanning and assembly of multiple GDSII databases for Multi-Chip Modules (MCM) and Multi-Project Chips or Wafers (MPC or MPW). At the same time Xyalis has updated its complete suite of GDSII utilities. Designed to reflect feedback from its customers, Xyalis’ tools meet market needs and closely track technological developments. MCM and MPW are becoming more economically viable due to the increasing cost of masks, density improvement provided by the leading process technologies and popular MPW programs launched by independant foundries. However, MCM and MCP require the floorplanning and assembling of the different blocks or designs. These layouts are generally developped by different teams and creates large databases that cannot be efficiently managed by current layout editor or IC floorplanner. Moreover, MCM and MCP assembly must take into account manufacturing issues and specific requirements such as sawing lines and metal filling. GTmuch, a graphical tool dedicated for floor-planning and assembling blocks of GDSII data, allows engineers to detect database consistency problems before tape-out and is targeted for multi-chip modules and multi-project wafers. GTmuch not only provides fast layout processing but also addresses all the manufacturing requirements, optimizes the final die size and eases documentation of MPC and MPW.

The main features of GTmuch are:

  • Automatic compaction and alignment of chips
  • Automatic placement with area optimisation and/or sawing lanes optimisation
  • Database merging with optional renaming of cells
  • Automatic metal filling for density uniformisation
  • Automatic documentation
  • Works on various platforms (Sun, HP, Windows, Linux)

The new release adds the following :

  • 64 bits support on SOLARIS 2.8 and HPUX 11 for files of more than 2Gb
  • Possibility to group and freeze a subset of chips and manipulate them as easily as a single chip
  • Possibility to build arrays of chips
  • Support of “cut & paste” through different projects for reuse
  • Automatic exclusion of sawing lanes in metal filling process
  • Intelligent selection of chips within an assembly
  • Many GUI enhancements

Along this new GTmuch release, Xyalis also introduces a new release of GTsuite, a comprehensive set of GDSII manipulation tools for chip finishing and validation. With the emergence of SOC and increasing design complexity, current designs generate larger layout databases that become very difficult to process. For instance, System-On-Chip (SOC) designs with Hard IP blocks increase the complexity of the tape-out as IP blocks must be instantiated during chip finishing. Time to manufacturing of critical designs is increased because existing Multi-Purpose layout finishing tools, such as Design Rules Checkers are no longer able to address the issues of today’s largest designs. GTsuite is dedicated to Chip Finishing of the largest designs with minimum memory, disk requirements. GTsuite turns final processing and painful last minute adjustments to your GDSII database easy and safe.

The major new features of other GTsuite tools are :

  • GTviewer (powerful GDSII viewer) : display speed increased at least 5 times
  • GTlayer (GDSII layers translation and removal tool) : possibility to flatten hierarchy
  • GTcheck (GDSII integrity verificator and information extractor) : automatic computation of design grid.
  • GTmerge (GDSII databses and libraries merging tool) : support of multiple libraries including hierarchy.
  • GTtiler (Automatic dummies insertion for density uniformisation) : computation of density before and after process.

All tools are now available in 64 bits binary format for huges databases. All new versions are available on Xyalis september CDrom or from our website http://www.xyalis.com/ An evaluation license is available upon request. Prices range from $5,000 to $100,000.