Resources Library - Publications
Resources, white papers, articles
NanoSkills[Nan, 2012] is a project belonging to Leonardo program and sponsored by EACEA[EAC, 2012]. Its is developed by a consortium of both universities and SMEs. The role of the the universities is to develop online courses on nanoelectronics while the SMEs will help to setup a professional environment and to validate it. The goal of the project is to provide master level courses to both students and employees. The content of the courses should bring the learners, the skills expected by the industry to work on the most advanced topics of nano-electronics. In order to fulfill the industry needs, a preliminary analysis has been performed among the various customers. This paper describes this analysis. We will fist detail the elaboration of the questionnaire. We will then review the answers, and finally analyze the results in order to select the most important courses to be developed.
Nowadays, two different methodologies are used to address the CMP issues. On one hand, we find basic design oriented methods consisting of reaching a minimal density of geometries in the design. On the other hand we find model based approaches in which complex process related parameters are used. This makes these techniques, either not accurate or not usable by designers. In both cases there is no efficient monitoring of the CMP effect through Process Control Modules.
This paper presents a new methodology to improve CMP process yield from the designer side. A prediction function of metal thickness variations due to CMP is established thanks to specific test structures. A method to monitor the CMP process evolution at no cost is presented and finally a technique for using the prediction function to drive metal filling procedure is described.
Some chip manufacturing steps lead to non-negligible process variation at wafer level. Typically, chemo-mechanical planarization, known as CMP, is a non-homogeneous process and thickness variations can be measured depending on the distance from a specific die to the wafer center. These variations have an impact on chip performances and thus on the final yield. This effect may be amplified by the fact that thickness variations on processed wafers introduce focus issues during later photo-lithography steps. Original chip layouts are modified by inserting dummies to correct thickness variation issues due to CMP, but these correction are based on models only depending on average values. In this paper, we propose a methodology to replace a single instance of the field written on the mask by multiple instances of this field as commonly used for Multi Layer Reticles. In the described methodology, each field of a same mask does not consist in different layers of the same chip, but of an optimized image of the same layer of the chip.