High Performance Planarization and CMP
Deep sub-micron technologies require that process-related issues be taken into account during the design stage. A Chemical-Mechanical Polishing (CMP) step has been adopted during manufacturing process to flatten the wafer surface between each metal layer. As metal density variations negatively impact the CMP process and result in lower manufacturing yield, “dummy tiles” must be inserted to unify the density of each metal layer.
XYALIS offers dummy fill engines for the most advanced manufacturing processes, maximizing CMP yield with accurate tile insertion, and minimizing parasitic effects by limiting the number of tiles and their parasitic effect on critical active geometries.
Thanks to patented dummy tile insertion algorithms, XYALIS dummy fill solution address the most advanced needs of the semiconductor industry, taking into account topology density and roughness to calculate fill, keeping away tiles from critical paths to reduce parasitics, automatically resizing or connecting tiles to meet density requirements.
XYALIS one-pass algorithms and highly optimized output database, allow designers to run metal fill as often as necessary during the design process to take into account the impact of tile insertion on the chips behavior and performance and avoid faulty tape-outs.