XYALIS, in collaboration with Mosis, has published an article about “Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns”.

This result has been presented in the SPIE Advanced Lithography + Patterning, San Jose, California, USA, February 26th – March 2nd, 2023.

Abstract

The demand for high-performance semiconductor products has increased with no end in sight since the early days of this industry. This product demand phenomenon has continuously pushed the technological frontier to a moving limit for enhanced performance leading to the need for an ever-thinner die for advanced 3D packaging.

Die down to a thickness of 5 µm is feasible. The thin die approach may lead to a heterogenous stack of 50 dies, leading to the highest available performance with an unprecedented form factor. One significant barrier is the fragility of the thin die and its impact on yield, reliability, and costs.

A comprehensive crack propagation and thin die fragility model that is rich in both theory and application is presented. In this paper, we show an MPW reticle placement with automation that inserts new and specific crack-stop patterns to mitigate the risk of die wafer fracture. We show this method to address die fracture from both the front and the back sides of the wafer, yielding an authentic 3D approach to crack-stop.

Access to the abstract

ACM Reference Format:
Authors:
From The MOSIS Service (United States): Jaime Bravo, Lifu Chang, Joshua Zusman
From XYALIS (France): Philippe Morey-Chaisemartin, Eric Beisser, Frederic Brault
“Minimizing die fracture in three-dimensional IC advanced packaging wafer thinning process by inserting polyimide patterns”, Proc. SPIE 12495-37, Advanced Lithography + Patterning, (1 March 2023) – http://dx.doi.org/10.1117/12.2657011