XYALIS at DAC conference 2018 : booth #1610

Leveraging years of leadership in layout finishing, XYALIS introduces a unique geometry-based signature enabling a safe and fast traceability process. It is tailored to handle the multiplicity of design styles and representation standards specific to electronic design while protecting intellectual property during exchanges.

As exchanges of layout descriptions between teams involved in modern integrated circuit (IC) development and production increase in terms of rate, value, and size, it becomes critical to implement a secure, reliable, and efficient information exchange flow between collaborating companies and teams. 


Electronic designs are not well suited to traditional file control systems. The same version of a design may come in different formats, especially as companies move from GDSII to OASIS for memory and processing speed reasons. Worse, with the flexibility that layout formats allow on the structure and organization of a layout file, a single design (identical cells instantiated in an identical hierarchy) may end up being described by two totally different files that will result in two very different file-based signatures. 


To address the specific demands of electronic design version tracking, XYALIS is introducing the geometry-based signature, a unique file which associates each technology layer with a checksum based on the geometric envelop of the layer’s polygons. This signature file is independent of the layout file format and of the design description strategy.

While until now, comparing a version of a design to its reference version required to perform a XOR between the two layouts, a time-consuming process necessitating an access to both layout files, it is now possible to quickly compare a layout file to XYALIS reference geometry-based signature. The reference layout file doesn’t need to be transmitted anymore, thus improving the security of intellectual property.

See us at DAC 2018

XYALIS will demonstrate the geometric-based signature, and its database file integrity control flow which increases the performance and security of electronic design exchanges, by focusing on what matters, the geometric description of the design at the next Design Automation Conference, in San Francisco, June 25-27, on booth #1610.

  • Monday, June 25 from 10:00 am to 6:00 pm
  • Tuesday, June 26 from 10:00 am to 6:00 pm
  • Wednesday, June 27 from 10:00 am to 6:00 pm

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