Products
Posts
- April’22: New Release
- Automatic Mask Pattern Localization
- Beyond tape-out: open the dark side
- Covid-19
- DelfMEMS selects XYALIS’s MDP tools
- Design Driven Dummy Filling
- Geometric based signature – EU patent issuance
- Geometric based signature – US patent issuance
- Geometric based signature patent
- Geometry-based signature for layout database comparison
- Mar’20: What’s new in XYALIS tools release
- May’21: New Release
- Minimizing die fracture in 3DIC die integration
- Minimizing die fracture in three-dimensional IC
- MPW Automatic Placement
- Nanoform long-term archiving solution
- NanoSkills
- NanoSkills access
- New Mask Data Prep Distribution
- New release of our hybrid dummy fill tool, GTstyle
- November’22: New Release
- Oct’19: What’s new in XYALIS tools
- Oct’20: New Release
- Reducing stress effects on multi-project-wafer reticles
- Single-pass frame generation for multi-layer 3D circuits
- Soft Biz Day award for GTnano
- Spie 2020 – Baccus : Maskset automatic flow
- STMicroelectronics QUALIFIES XYALIS GTSMOOTH OXIDE THICKNESS ESTIMATION TECHNOLOGY
- XYALIS and SII NanoTechnology announce strategic collaboration
- XYALIS announce a new release of GTsmooth its density estimator and tiling engine
- XYALIS announce an Advanced Methodology for Building CMP Models
- XYALIS announced today GTstyle. The next generation tool for Dummies Filling at 65nm and below
- XYALIS announced today OASIS support for its family of layout finishing tools
- XYALIS announces GTsmooth, The First Hybrid Metal-Fill Tool
- XYALIS at DAC Conference 2013
- XYALIS at DAC conference 2014
- XYALIS at DAC Conference 2015 : booth #2606
- XYALIS at DAC Conference 2016 : booth #1918
- XYALIS at DAC conference 2017 : booth #2129
- XYALIS at DAC conference 2018 : booth #1610
- XYALIS at DAC conference 2019 : booth #946
- XYALIS at DAC conference 2021 : booth #1407
- XYALIS at DAC conference 2022 : booth #2455
- XYALIS at DAC conference 2023 : booth #2455
- XYALIS at DAC Conference 2024: #booth 2516
- XYALIS at Date Conference 2013
- XYALIS at JEVeC conference 2023 in Japan
- XYALIS at SPIE Advanced Lithography Conference 2013
- XYALIS at SPIE BACCUS 2012
- XYALIS at SPIE Photomask 2013
- XYALIS at SPIE Photomask 2019: Large Dies Stitching
- XYALIS at SPIE Photomask 2022 : Single-pass frame generation for multi-layer 3D circuits
- XYALIS at SPIE Photomask conference 2016
- XYALIS at SPIE Photomask conference 2017
- XYALIS at SPIE Photomask conference 2023
- XYALIS at SPIE Photomask conference 2024
- XYALIS Brings Cost Reduction To Mask Design
- XYALIS GTstyle dummy fill engine achieves unsurpassed performance for 28nm highly parallel processor
- XYALIS marks North American Operations expansion with official opening of an office in San Jose
- XYALIS new version of GTmuch makes multi-chip modules and multi-project wafers even easier
- XYALIS new version of GTmuch makes multi-chip modules and multi-project wafers even easier
- XYALIS offers unprecedented capabilities with its New Multi-Project Wafer Preparation and management System
- XYALIS supports Fahrenheit2451 project
- XYALIS unveils Hartroid: A Strategic Initiative to Counter Hardware Trojans in Defense Systems
Pages
Resources Library
- Automatic pattern localization across layout database and photolithography mask
- CMP Monitoring and Prediction Based Metal Fill
- Customize your editor for XYALIS files
- Design Driven Dummy Filling
- European MEDEA+ CRYSTAL Project: “DFM Photomasks inputs for EDA workflow” Task Force
- From GDSII to OASIS
- Glossary
- Highlights of XYALIS tools in Kalray design flow
- Industry needs analysis for developing new skills in nano-electronics
- Is it time to switch to OASIS.MASK ?
- Large dies stitching: A Technical and Cross-Functional Teams Challenge
- Layout Database File Control: The Missing Link
- Layout finishing of a 28nm, 3 billions transistors and multi-core processor
- Minimizing die fracture in three-dimensional IC
- Reducing stress effects on multi-project-wafer reticles
- Single-pass frame generation for multi-layer 3D circuits
- Using a Mask Rule Checker as an Electrical Rule Checker
- Versions history
- Yield optimization through MLR techniques
