XYALIS GTstyle dummy fill engine achieves unsurpassed performance...
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XYALIS GTstyle dummy fill engine achieves unsurpassed performance for 28nm highly parallel processor
Grenoble, October 29th, 2012 – XYALIS and KALRAY announce that XYALIS GTstyle has successfully addressed the advanced dummy fill challenges of KALRAY’s MPPA-256 manycore processor, designed using state of the art 28nm process.
With its complex process rules from both analog parts requiring dedicated dummy fill procedures and large digital areas with timing and race condition constraints, KALRAY’s most advanced manycore processor was a challenging with respect to the layout finishing.
“This was an exciting challenge to successfully interface our tools into a standard 28nm Design Flow” said Philippe Morey-Chaisemartin, XYALIS’s CTO.
Thanks to unsurpassed performance and functionality, XYALIS GTstyle dummy fill engine achieved fully customized dummy generation for both analog and digital parts of the processor design. It was able to handle 28nm design rules as well as all specific designer requirements, such as automatic dummy mirroring in critical parts of the design. XYALIS GTstyle flexibility enabled a fast setup with an easy definition of the Design Rule Checker (DRC) compliant rules as well as KALRAY’s constraints not supported by the foundry provided procedures.
“The dummy generation is always a challenge for both critical analog circuit and large digital design” said François Jacquet, Physical Design team manager. “XYALIS advanced software tools allow us to effectively manage this challenge thanks to its ease of use and high capacity for effective analysis”.
In addition to GTstyle, KALRAY has used a set of XYALIS distributed layout finishing tools before tapeout.
SmartMRC, an advanced Mask Rule Checker developed by SIINT (Japan) and distributed by XYALIS in Europe and North America, was used on the final database to detect line interruptions in upper metal layers that could lead to power drop failures, a design flaw that cannot be exposed by other DRC tools. SmartMRC has allowed a thorough and fast validation of the whole chip power grid.
“Thanks to the effectiveness of the XYALIS’ tools and to the responsiveness of their team, we managed to produce the tapeout of our MPPA-256 chip on time“, added Joël Monnier, CEO of KALRAY.
XYALIS GTcheck was used for final database qualification and detected off-grid coordinates that could have lead to mask writing issues, and XYALIS GTlabel was used to generate DRC and mask compliant texts and labels.
With over 10 years of expertise in dummy fill and layout finishing software, XYALIS confirms its technical leadership in this domain by enabling a successful tapeout at the 28nm technology node.
More technical details can be found at: /resources-library
Established in 1998, XYALIS is headquartered in Grenoble, and is a leading specialist in layout finishing and GDSII/OASIS processing software. Designed to solve problems which the major ECAD companies do not address, the range consists of a complete suite tools for Mask Data Preparation and for dummy/metal filling. For more information, please visit .
Created in 2008, Kalray is a fabless semiconductor and software company which develops, markets & sells a new generation of manycore processors for low to medium volume high performance applications. Typical applications are: image, audio and signal processing, scientific computing, communications infrastructures, control command. Led by Joël Monnier, former vice president of STMicroelectronics, Kalray employs 55 engineers and is backed by French investment funds, local funds, private investors, and OSEO, a French public-sector institution who finance innovative projects brought by SME’s. Kalray’s technology is developed within a collaboration with the CEA, including a joint laboratory of 30 engineers. For more information about Kalray please visit http://www.kalray.eu.